7 Segments display on my Spartan

I decided to start my VHDL review with the 7 segments display controller for the Spartan 3 FPGA Board. I have to admit that I cheated a little bit and reused most of the original code I used for my class. I just added a little extra functionality and comments to my code. Before I post the code, let's review the way this 4 digit display works.

Now, you may have thought there should be 7 signals to drive each of the 4 digits and 4 for each of the possible decimal points, a total of 32. However, there are only 12 signals that control the display: 7 for the segments, 1 for the decimal point and 4 to select which one of the 4 digits is active. This is a clever way to save 20 inputs and adds just very little difficulty to the implementation. Because of this, only one digit can be on at a time. So... how come we see all 4 on? It's just a matter of turning them on and off in a cycle so fast that the human eye won't notice when they're off. If we slow down the cycle enough we can see it:

Display slowed down using a 26 bit counter

The way I have adjusted the speed of the cycle is by making a counter large enough (16 bits for the final version) so that the 2 most significant bits take a while to change when the number is being increased by one every clock cycle. Those two bits are the select signals for the multiplexers that pick one of the digits and its value to display. I tried to see what happened if the counter was smaller and noticed that the digits started to get all blurred together. After fixing that, I took a picture of the working display:

"Finished product"

I almost forgot to mention: all the signals for the display are "Low asserted", which means that "ON" is 0 instead of 1 and "OFF" is 1 instead of 0.

Finally, HERE is the VHDL code and its corresponding .ucf file(the one that matches the signal names to on the code to the board signals.